1. Field of the Invention
The present invention relates to a dielectric isolation type semiconductor device and a method for manufacturing the same, in which a pair of semiconductor substrates are bonded to each other through a buried or embedded oxide film. More particularly, the invention relates to a dielectric isolation type semiconductor device and a manufacturing method therefor, in which a porous oxide film is formed in contact with and at a location right under a buried or embedded oxide film.
2. Description of the Related Art
In the past, a variety of dielectric isolation type semiconductor devices have been proposed (for instance, see a first patent document: Japanese patent No. 2739018 (FIGS. 52 through 57)).
As shown in FIGS. 52 and 53 in the first patent document, a semiconductor substrate of a dielectric isolation type semiconductor device is provided on its upper surface and lower surface with a dielectric layer and a rear surface electrode, respectively, with an n− type semiconductor layer being arranged on an upper surface of the dielectric layer.
In addition, the dielectric layer serves to dielectrically isolate the semiconductor substrate and the n− type semiconductor layer from each other, and a first insulating film defines the n− type semiconductor layer in a predetermined range.
An n+ type semiconductor area of a relatively low electric resistance value is formed on the upper surface of the n− type semiconductor layer in the predetermined range defined by the first insulating film, and a p+ type semiconductor area is also formed so as to surround the n+ type semiconductor area. Moreover, a cathode electrode and an anode electrode are connected with the n+ type semiconductor area and the p+ type semiconductor area, respectively, and the cathode electrode and the anode electrode are electrically insulated from each other by a second insulating film.
Also, as shown in FIG. 54 in the first patent document, if both the anode electrode and the rear surface electrode are set to 0V with a positive voltage applied to the cathode electrode being gradually increased there will develop a first depletion layer that extends from a pn junction between the n− type semiconductor layer and the p+ type semiconductor area. At this time, since the voltage of the semiconductor substrate is fixed to ground potential and acts as a field plate through the dielectric layer, a second depletion layer in addition to the first depletion layer develops so as to extend from an interface between the n− type semiconductor layer and the dielectric layer in a direction toward the upper surface of the n− type semiconductor layer.
In this manner, the first depletion layer become able to easily extend toward the cathode electrode owing to the extension of the second depletion layer, whereby an electric field at the pn junction between the n− type semiconductor layer and the p+ type semiconductor area is alleviated. This effect is generally known as a RESURF (Reduced SURface Field) effect.
Further, as shown in FIG. 55 in the first patent document, let us assume that in the distribution of electric field strength in a cross section at a location sufficiently apart from the p+ type semiconductor area, the vertical width of the second depletion layer is represented by x; the thickness of the dielectric layer is represented by t0; and the upper surface of the n− type semiconductor layer is made to correspond to the origin of the axis of abscissa. In this case, a full voltage drop V in the above cross section is represented by the following expression (3).V=q·N/(ε2·ε0)×(x2/2+ε2·t0·x/ε3)  (3)
Here, note that in expression (3) above, N is an impurity concentration [cm−3] of the n+ type semiconductor layer; ε0 is a dielectric constant [C·V−1·cm−1]; ε2 is the dielectric constant of the n− type semiconductor layer; and ε3 is the dielectric constant of the dielectric layer.
From expression (3) above, it is found that when the thickness t0 of the dielectric layer is increased while keeping the amount of full voltage drop V unchanged, the vertical width x of the second depletion layer is decreased. This means the RESURF effect becomes weaker.
On the other hand, under the condition that avalanche breakdown due to the concentration of electric field at the pn junction between the n− type semiconductor layer and the p+ type semiconductor area and the concentration of electric field at the interface between the n− type semiconductor layer and the n+ type semiconductor area does not occur, the dielectric strength of the semiconductor device is eventually determined by avalanche breakdown due to the concentration of the electric field at the interface between the n− type semiconductor layer and the dielectric layer at a location right under the n+ type semiconductor area.
In order to construct the semiconductor device so as to satisfy such a condition, the distance between the p+ type semiconductor area and the n+ type semiconductor area has only to be set very long so that the thickness d and the impurity concentration of the n− type semiconductor layer can be optimized.
For the above condition, it is generally known that when depletion takes place from the interface between the n− type semiconductor layer and the dielectric layer to a front surface of the n− type semiconductor layer, the concentration of the electric field at the interface between the n− type semiconductor layer and the dielectric layer just satisfies the avalanche breakdown condition, as shown in FIG. 56 in the first patent document. In this case, the depletion layer reaches the n+ type semiconductor area, and depletes the entire n− type semiconductor layer.
A dielectric strength V under such a condition is represented by the following expression (4).V=Ecr·(d/2+ε2·t0/ε3)  (4)
Here, note that in expression (4) above, Ecr is a critical electric field strength that causes avalanche breakdown, and the thickness of the n+ type semiconductor area is ignored.
As shown in FIG. 57 in the above-mentioned first patent document, an electric field strength at a boundary between the n− type semiconductor layer and the dielectric layer (i.e., a position at a distance d from the origin to the electrode side) in the vertical distribution of electric field strength in a cross section right under the n+ type semiconductor area reaches the critical electric field strength Ecr.
In case where the dielectric strength V of the semiconductor device is calculated with the n− type semiconductor layer being formed of silicon, and the dielectric layer being formed of a silicon oxide film, d=4×10−4 and t0=2×10−4 are adopted as general values for the distance d and the thickness t0, respectively.
Moreover, in this case, the critical electric field strength Ecr, though influenced by the thickness d of the n− type semiconductor layer, is represented by about Ecr=4×105. When this critical electric field strength Ecr (=4×105), ε2(=11.7) and ε3(=3.9) are substituted in the above expression (4), the dielectric strength V is represented by the following expression (5).V=320 V  (5)
Accordingly, when the thickness d of the n− type semiconductor layer increases by 1 μm, a voltage rise or increase ΔV represented by the following expression (6) is obtained.ΔV=Ecr×0.5×10−4=20[V]  (6)
In addition, when the thickness t0 of the dielectric layer increases by 1 μm, the voltage rise or increase ΔV represented by the following expression (7) is obtained.ΔV=Ecr×11.7×10−4/3.9=120 [V]  (7)
As will be clear from the results of the calculations of the above expressions (6), (7), a rise or increase in the dielectric strength is greater when the dielectric layer is set thick than when the n− type semiconductor layer is set thick, and hence it can be seen that in order to raise or increase the dielectric strength, it is effective to set the dielectric layer thick.
In addition to this, setting the n− type semiconductor layer thick makes it necessary to employ a technique of etching deeper trenches so as to form the first insulating film, which requires development of a new technology and hence is not desirable.
On the other hand, when the thickness t0 of the dielectric layer is increased, the extension x of the second depletion layer becomes small, as stated above, thus resulting in reduction in the RESURF effect. That is, the concentration of the electric field at the pn junction between the p+ type semiconductor area and the n− type semiconductor layer increases, whereby the dielectric strength will be limited by the accordingly increased probability of avalanche breakdown at this pn junction.
Thus, as stated above, the known dielectric isolation type semiconductor device has a problem in that the dielectric strength of the semiconductor device is limited depending upon the thickness t0 of the dielectric layer and the thickness d of the n− type semiconductor layer.